vvsandClaude Opus 5 441373800b PREREG_flat_analogy_mem outcome (decided on the smoke, all 199 problems): NOT accepted. Remembering the analogy until the next flag: CHA 2635 -> 2552 (G2: 2625 -> 2548; flat fun3-6 1234 -> 1151, M4 holds) but APS 2806 -> 2814 (G2: 2782 -> 2787 = Chandrupatla, M2 fails) - the extra false entries. Server regression x2: 1069 passed, 1 failed = the expected paper-number check. ...

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>

2026-09-21 15:06:37 +01:00

..

__init__.py

baseline: the published sim-numerics artifact as it stands (490 tests, verify_article.py checks all 72 paper numbers against sweep_full.json)

2026-09-20 22:38:17 +01:00

baselines.py

Sign tests by product underflowed: FIXED everywhere (branch, not master - the paper is not yet updated). FA * fnew < 0.0 with FA ~ -1e-200, fnew ~ 1e-150 is -0.0 and '-0.0 < 0.0' is False, so on flat functions (x^19) the bracket update moved the wrong end, the root left the bracket and the run still reported convergence - the proposed rule returned 4.9e-9, bisection 3.5e-9, ITP 1.6e-8 with a claimed 1e-12 bracket; the 1e-6 harness scored them solved. Same defect in our bisection, false-position family, Ridders, Brent, ITP and twelve copies in stage scripts, simroot/sim.py and one test; all replaced by _opposite / _same_sign, pinned by test_sign_underflow.

2026-09-21 12:49:01 +01:00

pure.py

PREREG_flat_analogy_mem outcome (decided on the smoke, all 199 problems): NOT accepted. Remembering the analogy until the next flag: CHA 2635 -> 2552 (G2: 2625 -> 2548; flat fun3-6 1234 -> 1151, M4 holds) but APS 2806 -> 2814 (G2: 2782 -> 2787 = Chandrupatla, M2 fails) - the extra false entries. Server regression x2: 1069 passed, 1 failed = the expected paper-number check.

2026-09-21 15:06:37 +01:00

sim.py

Sign tests by product underflowed: FIXED everywhere (branch, not master - the paper is not yet updated). FA * fnew < 0.0 with FA ~ -1e-200, fnew ~ 1e-150 is -0.0 and '-0.0 < 0.0' is False, so on flat functions (x^19) the bracket update moved the wrong end, the root left the bracket and the run still reported convergence - the proposed rule returned 4.9e-9, bisection 3.5e-9, ITP 1.6e-8 with a claimed 1e-12 bracket; the 1e-6 harness scored them solved. Same defect in our bisection, false-position family, Ridders, Brent, ITP and twelve copies in stage scripts, simroot/sim.py and one test; all replaced by _opposite / _same_sign, pinned by test_sign_underflow.

2026-09-21 12:49:01 +01:00